Vivado Simulation (No Testbench)#
Implementation Steps#
- Create a new project and add your own Verilog file
After adding, Vivado will automatically recognize the module in the file.
- Create a block design file and add modules
There may be warnings before adding, wait for a while.
- Right-click again and click "Add IP" to add the following modules
Double-clicking on this module allows you to set various parameters
- Run auto-connection and select the clock source added above
![image-20231125111152197](/_next/image?url=https%3A%2F%2Fraw.githubusercontent.com%2Fmoerjie%2FmyPic%2Fimg%2Fimg%2F202311251111241.png&w=3840&q=75)
- Right-click on the floating pin and select the following option to create a port
- In the left source column, right-click on 1 and select the option at 2 to convert the bd file to a .v file
- Right-click on the generated new file and set it as the top file
- Run the simulation and you can see the simulation results
![image-20231125113843876](/_next/image?url=https%3A%2F%2Fraw.githubusercontent.com%2Fmoerjie%2FmyPic%2Fimg%2Fimg%2F202311251138968.png&w=3840&q=75)
Summary#
If the simulation clock module is added, there may be errors when performing RTL analysis and synthesis. It is estimated that this module can only be used for behavioral-level simulation.
As I have just started using Vivado, I am not familiar with many operations. If there are any errors, please feel free to point them out.