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Vivado simulation (without testbench)

#FPGA37
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This post is translated from Chinese into English through AI.View Original
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This is a guide on how to perform Vivado simulation without a testbench. The steps include creating a project, adding Verilog files, creating a block design, adding modules, setting parameters, running automatic wiring, creating ports, converting the block design file to a .v file, setting it as the top file, and running the simulation. The author notes that adding a simulation clock module may cause errors during RTL analysis and synthesis. They also mention that they are new to using Vivado and welcome any corrections.

Vivado Simulation (No Testbench)#

Implementation Steps#

  1. Create a new project and add your own Verilog file

image-20231125110055893

After adding, Vivado will automatically recognize the module in the file.

  1. Create a block design file and add modules

image-20231125110528510

There may be warnings before adding, wait for a while.

image-20231125110236315

  1. Right-click again and click "Add IP" to add the following modules

image-20231125110856237

Double-clicking on this module allows you to set various parameters

image-20231125110953701

  1. Run auto-connection and select the clock source added above

image-20231125111057636

image-20231125111152197
  1. Right-click on the floating pin and select the following option to create a port

image-20231125111342659

  1. In the left source column, right-click on 1 and select the option at 2 to convert the bd file to a .v file

image-20231125111720073

  1. Right-click on the generated new file and set it as the top file

image-20231125111950383

  1. Run the simulation and you can see the simulation results
image-20231125113843876

Summary#

If the simulation clock module is added, there may be errors when performing RTL analysis and synthesis. It is estimated that this module can only be used for behavioral-level simulation.

As I have just started using Vivado, I am not familiar with many operations. If there are any errors, please feel free to point them out.

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