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Cyclone III Internal Resources

#FPGA41
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This document provides an overview of the internal resources of the Cyclone III FPGA. It includes information about logic elements, logic array blocks, memory blocks, embedded multipliers, and clock networks. The Cyclone III FPGA contains 15,408 logic elements, 56 M9K memory blocks, 56 18x18 multipliers, and 4 PLLs. The logic elements are the smallest units in the FPGA and can be configured for various logic functions. The logic array blocks consist of 16 logic elements and are used for local interconnects and register chains. The memory blocks are composed of M9K memory units and can be configured for various memory functions. The embedded multipliers support digital signal processing operations. The clock networks and PLLs provide clocking and synchronization capabilities.

Overview of Cyclone III Internal Resources#

[toc]

pitfC2n.png
The main control chip used in the Altera DE0 I am using is EP3C16F484C6. From the above figure, it can be seen that it includes 15,408 logic elements, 56 M9Ks, 56 18×18 multipliers, 4 PLLs, and other resources.

Logic Elements and Logic Array Blocks#

LE#

LE is the smallest logic unit in the FPGA, which provides advanced functions for efficient logic utilization. The structure of LE is shown in the following figure:
pitho6I.png

  • LUT: Used to perform the required logic functions of the user. The lookup table of Cyclone III is 4-input 1-output, which can perform any 4-input 1-output combinational logic.
  • Programmable Register: Can be configured as D flip-flop, T flip-flop, JK flip-flop, etc. Each register contains 4 input signals: data signal, clock signal, clock enable, and reset signal.

LE has two operating modes:

  • Normal mode: Suitable for general logic operations.
  • Arithmetic mode: Used to implement adders, counters, accumulators, comparators, etc.

LAB#

Each LAB consists of the following elements:

  1. 16 LEs
  2. LAB control signals
  3. LE transfer chain
  4. Register chain
  5. Local interconnect

Local interconnect is used to transmit signals between LEs within the same LAB; register chain is used to pass the output of one LE to adjacent LEs.
The structure of LAB is shown in the figure below:
pit4Ruq.png

LAB Interconnects#

LAB local interconnect is driven by column and row interconnects within the same LAB and LE outputs. Adjacent LABs, PLLs, M9K RAM blocks, and embedded multipliers from left to right can also be directly linked to drive the local interconnect of the LAB. Direct linking minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive up to 48 LEs through fast local and direct link interconnects.
The direct connection is shown in the figure below:
pit5Za8.png

Memory Blocks#

The embedded memory structure consists of M9K memory blocks, which can be configured to provide various memory functions such as RAM, shift registers, ROM, and FIFO.
pit50MR.png

The memory unit of M9K is 9k ==bit==, not 9k ==byte==, and 1k space in 9k is used for verification and other functions. The actual available space is 8kbit.

Memory mode#

pitI9oT.png
M9K memory blocks do not support asynchronous memory input.

Clocking mode#

pitIcmq.png
When using the Read or Write mode, if the same address is read and written, the output read data is unknown. To make the output data a deterministic signal, you need to use the single-clock mode or IO-clock mode and select the appropriate read and write operations in the MegaWizard Plug-In Manager.

Violating the setup and hold time of the memory block input registers during read and write operations may result in memory corruption.
Asynchronous clear is only available on read address registers, output registers, and output latch registers.

The relationship between Memory mode and Clocking mode is shown in the figure below:
pito84U.png

Embedded Multipliers and Digital Signal Processing Support#

Multiplier Structure#

piN8jIg.png

  • The input data can be sent to the input register or directly input to the multiplier. The two input signals are independent of each other. For example, signal A can be sent to the multiplier through a register, while signal B can be directly sent to the multiplier.
  • Depending on the bit width and operation mode of the multiplier, a single multiplier can perform one or two parallel multiplication operations.
  • If both input signals are unsigned numbers, the output data is also an unsigned number. If either one is a signed number, the output result is a signed number.

Clock Networks and PLLs#

image-20231121103548768

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