Introduction to AXI-STREAM#
Concept#
AXI-Stream bus is an efficient and simple data transfer protocol, mainly used for high-throughput data streaming scenarios. Compared to traditional AXI bus, AXI-Stream bus is simpler and lighter. It transfers data from one module to another without the need for addresses, making it suitable for applications that require high-speed data transfer.
Partial Terminology#
- Transfer: Transfer based on the TVALID and TREADY handshake protocol
- Packet: A group of data transmitted through axi-stream
- Frame: The largest byte combination, containing an integer number of packets
Interface Signals#
Signal | Description |
---|---|
ACLK | Global clock signal, rising edge effective |
ARSTn | Global reset signal, active low |
TVALID | Valid data driven by the host |
TREADY | The slave can receive data |
TDATA[(8n-1):0] | Bit width is a multiple of bytes |
TLAST | Indicates the boundary of the data packet |
TID | Identity identifier issued by the host, which works when there are multiple stream data transfers, used to identify different data streams |
Data transmission starts when both TVALID and TREADY are high on the rising edge of clk.
Since AXI-STREAM does not require address transmission and only performs simple sending and receiving, it reduces propagation delay.